Commit: ba4a04ae2f905e5c2775f1c9471c7391558d92b0
Parent: 5b27cb186161295388c2b9b67f14cd1646c31801
Author: Randy Palamar
Date: Thu, 10 Sep 2026 06:36:47 -0700
core: ensure pipeline barrier between DAS input writer and DAS
When TPW/VLS are beamformed the Filter shader (stage 0) outputs
directly into the portion of the buffer DAS is reading from. We
need to ensure that the previous round of DAS finishes before we
start writing the next batch into the buffer.
fixes #78
Diffstat:
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/beamformer_core.c b/beamformer_core.c
@@ -2,6 +2,8 @@
/* TODO(rnp):
* [ ]: backtrace dumping on SIGSEGV
* [ ]: cooperative shared memory loading in decode shader
+ * [ ]: refactor: when there are only two beamforming shaders switch back to ping pong input
+ * for DAS instead of fixed region to allow overlap with first stage
* [ ]: refactor: save filter parameters with rest of parameters, whole slot thing is dumb
* [ ]: upload previously exported data for display. maybe this is a UI thing but doing it
* programatically would be nice.
@@ -1579,7 +1581,7 @@ complete_queue(BeamformerCtx *ctx, BeamformWorkQueue *q, Arena *arena)
u64 output_pointer = ((i + 1) == (u32)das_index) ? pp_das_pointer : pp_output_pointer;
u64 input_pointer = (i == 0 && !special_handling) ? rf_pointer : pp_input_pointer;
- if (i != 0) gpu_command_pipeline_barrier(cmd, 0);
+ if (i != 0 || i == ((u32)das_index - 1)) gpu_command_pipeline_barrier(cmd, 0);
do_compute_shader(cmd, cp, frame, input_pointer, output_pointer, i, channel_offset);
gpu_command_timestamp(cmd);
}